In a computer system, devices are often coupled for communication using address signals transmitted over an address bus, and data signals transmitted over a data bus. Devices coupled for communication over the address and data busses typically contain circuitry for receiving addresses over the address bus, as well as circuitry for responding to the addresses and circuitry for transferring data over the data bus.
For example, a typical memory device receives addresses over the address bus, and in turn accesses an internal memory array which stores data. The memory device typically contains specialized circuitry for accessing the memory array, specialized circuitry for sensing the contents of the memory array, and circuitry for transmitting the data out of the memory array over the data bus.
Unfortunately, the device circuitry for receiving addresses over the address bus, for responding to the addresses, and for transferring data over the data bus typically draw a constant DC current even when not in use. For example, in a typical memory device, circuits for accessing the memory array, for sensing the contents of the memory array, and for transmitting the data from the memory array over the data bus draw DC current between address transitions on the address bus. As a result, the device consumes excessive DC current, which contributes to excessive power consumption of the system.
Some past devices have a standby mode for occasional use to reduce power consumption. Such devices require a CPU to switch the device into standby mode when the device is not needed. If the device then becomes needed, the CPU switches the device back to a normal mode. However, the standby mode is not suitable for reducing device power consumption between accesses during normal system operation. The overhead required for the CPU to switch modes of the device would dramatically reduce throughput to the device.